The present invention pertains generally to medical monitoring equipment, including equipment for providing a stimulus signal to a subject and for monitoring the response of the subject to the stimulus, and more particularly to methods and devices for synchronizing the time frames of the stimulus and response signals for analysis and display.
Medical monitoring involves monitoring the body of a subject to determine the state of health of the subject and to detect, identify, and diagnosis changes or abnormalities in the state of the body which may be indicative of problems. Medical monitoring may involve monitoring, for example, the motion of a subject""s body, temperature or chemical changes of the subject""s body, and/or audible or electrical signals generated by the subject""s body. For example, electroencephalography (EEG) is a form of medical monitoring wherein the electrical potentials of the subject""s brain are monitored by attaching electrodes to the subject""s scalp. In electromyography (EMG), electrical activity generated in the subject""s muscles is monitored using surface and/or needle recording electrodes. Medical monitoring may take place when a subject is at rest, in motion, or during the performance of a medical procedure. In some cases, medical monitoring involves monitoring the response of the subject to a stimulus. For example, EEG monitoring may be used to detect the electrical response of a subject""s brain to audible, visual, or electrical stimuli. Medical monitoring involving stimulus and response detection may be used in combination with EMG and various other medical monitoring methods as well.
A typical method of medical monitoring involving stimulus and response detection includes connecting a stimulator, e.g., via electrodes, to a subject, and placing monitoring electrodes, or other sensors, on the subject to detect the subject""s response to the stimuli provided by the stimulator. The stimulator is controlled by a stimulation controller, which provides a trigger signal to a stimulus generator to deliver stimuli of a desired magnitude, duration, and pattern to the subject. The electrodes or other sensors used to detect the response of the subject to the stimuli are connected to an amplifier device which amplifies the detected physiological response signals. The amplified response signals are, in turn, processed, analyzed, and displayed, typically using a microprocessor based monitor device.
In displaying and analyzing detected physiological response signals, it is important that accurate time frame synchronization between the stimulus and response signals is achieved. Such synchronization is critical to determining, for example, the delay time between the stimulus and the response. Such synchronization may be achieved where a stimulation controller, physiological signal amplifier, and analysis and display monitor system are contained in a signal device controlled by a single microprocessor, or by multiple microprocessors operating off of the same system clock. However, it is often desirable to employ stimulator, amplifier, and monitor devices which are implemented as separate devices, each having their own microprocessor control and system clock. This allows for modularity and separation of the medical monitoring system components. Modularity allows a variety of different stimulators, providing a variety of different types of stimulation, and a variety of different amplifier devices, for detecting a variety of different physiological response signals, to be used in combination with each other and with a given analysis and display monitor device. Separation allows the components of the medical monitoring system to be located remotely from each other. For example, during a medical procedure, it may be desirable to have the stimulator and amplifier devices separated from each other and from the analysis and display monitor device, which may be located in another room or even further from the site of the procedure. This minimizes the chance that the medical monitoring system will get in the way of the procedure, and allows the various medical monitoring system components to be positioned optimally such that information is made available to the appropriate personnel where required.
Where separate stimulator, amplifier, and display and analysis monitor devices are employed, and particularly where such devices are separated by a distance, synchronization between the stimulus and response signal time frames can be very difficult to maintain. Each such device is typically controlled by its own device controller, which is driven by its own local device clock. Even if the various device clocks are initially synchronized, and operate at the same nominal rate, divergence between the system clocks over time is inevitable. If the time frames in which the stimulus signal is applied and the response signals are detected cannot be synchronized, accurate display and analysis of the relationship between the stimulus and response signals is not possible. Currently, synchronization is achieved between independent stimulator, amplifier, and display and analysis monitor devices, each having its own independent device controller and device clock, by connecting the stimulator device to the display and analysis monitor device by a wire, and providing a signal on the wire when a stimulus signal is provided to a subject by the stimulator device. The distance over which such a wire can be run is limited. What is desired is a system and method for establishing a synchronous time frame between separate stimulator, amplifier, and monitor display and analysis devices in a medical monitoring system, wherein each such device may have its own independent device controller and device clock.
A general structure for a high speed serial bus for connecting together multiple devices, along with a protocol for sending data on the bus and for sharing the bus medium, is specified in IEEE standard 1394. (The official name of the standard is xe2x80x9cIEEE 1394-1995 Standard for High Performance Serial Busxe2x80x9d. It is published by the Institute of Electrical and Electronics Engineers (IEEE). IEEE 1394 has been implemented in commercially available products and sold, for example, under the trade name Fire Wire.) A 1394 bus structure is tree-like, having a xe2x80x9crootxe2x80x9d device, branching out to logical xe2x80x9cnodesxe2x80x9d in other physical devices. The root is responsible for certain control functions. The root device is chosen during initialization and, once chosen, retains that function as long as it remains connected to the bus. A 1394 network may include up to 63 nodes, with each node specified by a six-bit physical identification number. Multiple networks may be connected by bridges, to a system maximum of 1,023 busses. Combined, IEEE 1394 allows up to 64,449 nodes in a system with a maximum of 256 TB of memory space per node.
The IEEE 1394 bus structure is very flexible. Devices may be plugged into any available port on the bus. Devices can be hot-plugged, i.e., connected or disconnected while energized. The bus configures itself. There is no need to set address switches, and there are no hard wired addresses. Every time a node is added to or removed from the network, the bus""s topology is automatically reconfigured by the bus protocol. There can, however, be at most 16 hops between any two nodes, and devices may not be connected in such a way as to form loops. To maintain signal quality, standard IEEE 1394 bus cables should stretch no more than 4.5 meters between nodes. Physically, a 1394 bus cable terminates in a six-pin connector. The six pins are connected to a pair of power wires and two twisted-wire signal pairs. Each twisted pair is shielded, as is the entire cable. The power wires, which carry up to 1.5 A at 8.40 V, keep all parts of the bus alive even when some devices connected to the bus are unenergized. They also eliminate the need for an external power cable in some devices.
An IEEE 1394 bus is capable of transmitting large amounts of data very rapidly. The IEEE 1394 standard supports data rates of 100, 200, and 400 Mb/s. Depending on the capabilities of connected devices, one pair of devices can be communicating at 100 Mb/s, while another pair on the same bus exchanges data at 400 Mb/s. Additional data rates of 800 and 1600 Mb/s are proposed as extensions to the IEEE 1394 standard.
The IEEE 1394 protocol makes provision for two data-transfer modes, asynchronous and isochronous. Both handle data packets of varying length. In asynchronous mode, the packets are sent to explicit addresses and acknowledgments are returned. The asynchronous mode works well for traffic that does not require high data rates or precise timing, e.g., some control signals.
The isochronous mode broadcasts variable-length packets to all parts of the bus at regular intervals without acknowledgment. Isochronous operation is divided into time segments called isochronous cycles. An isochronous cycle begins when a bus Cycle Master (any isochronous-capable node, automatically selected during bus initialization) arbitrates for the bus and transmits a special asynchronous data packet, called a Cycle Start packet. Within this packet is the value of the Cycle Master""s clock counter. All devices on the bus receive this value, and update their own local bus clock counter value in response thereto, guaranteeing that the bus operates to a common time reference.
An IEEE 1394 bus interface is implemented by way of a conceptual bus framework having three layers, a physical layer, a link layer, and an application layer. The physical layer provides low-level access to the 1394 bus. IEEE 1394 devices may have one, two, or three connectors, each connected to a single physical layer chip. Cable power is typically extracted from the bus and used to power the physical layer chip, thereby maintaining the integrity of the bus while a 1394 connected device is turned off. The physical layer exchanges raw data and system clock signals with a link layer controller chip. The link layer is responsible for properly formatting isochronous and asynchronous data packets for transmission, and buffering incoming packets for processing by the application layer. Typical link layer controller chips provide host interfaces compatible with common microprocessors, PCI busses, and synchronous serial busses. The application layer formats packets for specific data transmission applications. Typically, a DSP or a RISC processor is employed as a host processor to the link chip. In addition, an IEEE 1394 bus includes a bus management system, which operates at all the serial bus layers in each device and performs some general control and housekeeping functions.
The present invention provides a system and method for establishing a synchronized time frame for stimulator, amplifier, and monitor devices in a medical monitoring system. In particular, the present invention provides a system and method for synchronizing the time frame of the delivery of a stimulus signal to a subject with the time frame of response signals received from the subject via an amplifier device and provided to a monitor device for analysis and display. By synchronizing the time frames of the stimulus and response signals, an accurate determination of the relationship between stimulus and response of the subject may be obtained, thereby improving a medical monitoring system""s analysis and display capability.
A medical monitoring system incorporating time frame synchronization in accordance with the present invention may include a stimulator device for providing stimulus signals to a subject, an amplifier device for receiving and amplifying response signals from the subject, and a monitor device for analyzing and displaying response data received from the amplifier device. The stimulator, amplifier, and monitor devices may be implemented as independent modular devices, wherein each such device is controlled by its own device controller, having its own independent device clock. (The amplifier and monitor devices may be combined in a single device.) The independent stimulator, amplifier and monitor devices of the medical monitoring system are connected together via a bus, such as an IEEE 1394 serial bus, which provides a periodic master bus cycle clock signal across the bus to guarantee that the bus operates to a common time reference. In accordance with the present invention, the master bus cycle clock signal provided across the bus is employed to provide a synchronized time frame reference for the stimulator, amplifier, and monitor devices. Multiple stimulator devices, providing various types of stimulation, amplifier devices, for receiving and amplifying various response signals, and monitor devices, for analyzing and displaying the response signals, may be connected together and time frame synchronized in this manner.
A stimulator device employed in a medical monitoring system in accordance with the present invention may include a stimulation controller, a stimulus generator, and a stimulus synchronization circuit, along with a bus interface circuit. The stimulator device is connected to a monitor device and an amplifier device via the bus interface. The stimulation controller provides a stimulation trigger pulse signal to the stimulus generator when a stimulus signal is to be provided to the subject. The stimulus signal may be an audible, visual, or electrical stimulus signal provided to the subject from the stimulus generator, via, e.g., electrodes placed on the subject. The response of the subject to the stimulus is received and amplified by the amplifier device. For example, electrodes may be placed on the subject to pick up EEG or EMG signals, which are received and amplified by the amplifier device. The amplified response signals are provided to the monitor device for analysis and display via the bus interface.
In accordance with the present invention, the stimulation trigger pulse signal provided by the stimulation controller to the stimulus generator is also provided to the stimulus synchronization circuit. The stimulus synchronization circuit generates a time frame synchronized stimulation trigger signal indicating the time when the stimulus signal is provided to the subject in a time frame which is synchronized with the amplifier and monitor devices. The time frame synchronized stimulation trigger signal is time frame synchronized using the master bus cycle clock signal provided by the bus connecting the stimulator, amplifier, and monitor devices together. The time frame synchronized stimulations trigger signal may be provided as a message via the bus interface to other devices on the bus for time frame synchronization of other signals (e.g., response signals) with the stimulus signal.
The stimulus synchronization circuit may include a phase lock loop (PLL) circuit which generates a local stimulus synchronization circuit clock signal that is phase locked to the master bus cycle clock signal provided by the bus connecting the stimulator device to the other system devices. The PLL may include, for example, a phase detector, wherein the, e.g., 8 kHz master bus cycle clock signal, from an IEEE 1394 bus, is compared to a local 8 kHz stimulus synchronization circuit clock signal to determine the phase difference therebetween. The output of the phase detection circuit is related to the phase difference between the master bus cycle clock and local clock signals. This signal is filtered, e.g., using a low pass loop filter, and provided to an oscillator, such as a voltage controlled crystal oscillator, which generates a local stimulus synchronization circuit clock signal which is thus driven by the PLL to be synchronized with the master bus cycle clock signal.
The stimulus synchronization circuit preferably generates a time frame synchronized stimulation trigger signal which indicates a point in time during a bus cycle, i.e., between master bus cycle clock signals, when the stimulation pulse trigger signal is provided from the stimulation controller to the stimulus generator to generate a stimulation signal which is provided to the subject. Since the master bus cycle clock is synchronized throughout the system, i.e., in the stimulator, amplifier, and monitor devices, such a signal provided by the stimulus synchronization circuit may be time frame synchronized with the other signals in the system, such as the physiological response signals received by the amplifier device, and may thus be used to provide accurate analysis and display of the relationship between the stimulus and response signals.
The time frame synchronized stimulation trigger signal may be derived by dividing the bus cycle into several equal segments. For example, the 125 microsecond cycle length of the IEEE 1394 bus may be divided, e.g., into twelve segments. The stimulation pulse trigger signal provided by the stimulation controller to the stimulus generator is employed by the stimulus synchronization circuit to generate the time frame synchronized stimulation trigger signal which indicates during which segment of the bus cycle the stimulation trigger signal was provided and, therefore, the time, in a synchronized time frame, when the stimulus was provided to the subject. This may be accomplished, for example, by dividing the local stimulus synchronization circuit clock signal, which is phase locked to the master bus cycle clock signal by the PLL, into various local clock signals having various frequencies. Selected ones of the various local clock signals are provided as inputs to a multi-bit register. The local clock signals are selected to form a varying multi-bit signal on the multi-bit register inputs which divides the master bus cycle into a plurality of equal segments. The stimulation pulse trigger signal from the stimulation controller is provided as a clock signal to the register, to latch into the register the state of the various local clock signals at the time the stimulation pulse trigger signal is provided to the stimulus generator. Thus, the output of the multi-bit register will be a multi-bit signal corresponding to the segment of the bus cycle during which the stimulus signal was applied. For example, for an IEEE 1394 bus, having a cycle frequency of 8 kHz, local stimulus synchronization circuit clock signals of 48 kHz, 24 kHz, and two signals with a frequency of 8 kHz and a duty cycle of one-third and wherein the active portion of the duty cycle is positioned in the center and at the end of the bus cycle, respectively, may be provided to the inputs of a four-bit register. This effectively divides the 8 kHz bus cycle into twelve equal segments. The stimulation pulse trigger signal from the stimulation controller is provided to the clock input of the multi-bit register. When the stimulation pulse trigger signal is provided, the states of the four local clock signals are latched into the register. The output of the register is thus a four-bit signal corresponding to the segment during the bus cycle at which the stimulation pulse trigger signal was provided. This time frame synchronized stimulation pulse trigger signal may be provided to the stimulator bus interface during the next bus cycle, to thereby provide the signal in a message to the other devices in the medical monitoring system. Since the time frame synchronized stimulation pulse trigger signal is synchronized with the master bus cycle clock signal, which is available to all devices on the bus, the stimulation pulse trigger signal may be time frame synchronized with other signals, including detected physiological response signals, in the medical monitoring system, for analysis and display.
Further objects, features, and advantages of the invention will be apparent from the following detailed description when taken in conjunction with the accompanying drawings.